The present invention relates to the field of semiconductors in general, and more particularly, to memory devices.
In general, a semiconductor memory devices may be classified as volatile memory devices that can lose stored information when power is turned OFF, and nonvolatile memory device that can retain stored information even when not powered.
A flash memory device is a type of nonvolatile memory device, and can have advantages of an erasable programmable read only memory (EPROM), and an electrically erasable programmable read only memory (EEPROM).
Flash memory devices may be divided into floating gate types and charge trap types according to the type of data storage layer constituting a unit cell. The flash memory devices may also be divided into stacked gate types and split gate types according to the structure of the unit cell.
Furthermore, flash memory devices may be divided into a NOR type and a NAND type. The NOR type flash memory device may have a high operation speed since it can independently control individual memory cells, but undesirably can require one contact per two cells and can have a large cell area. The NAND type flash memory device may be able to control a plurality of memory cells as a string, which can provide advantages in highly integrated applications.
Referring to FIG. 1, which is an equivalent circuit diagram illustrating a part of a general NAND type flash memory device, the NAND type flash memory device may include a cell array including a plurality of cell strings. Each cell string may include a ground selection transistor and a string selection transistor connected in series between a source region and a drain region, and a plurality of memory cells connected in series between the ground selection transistor and the string selection transistor. The cell array includes a plurality of ground selection lines (GSL), a plurality of string selection lines (SSL), and a plurality of word lines (WL) disposed between the string selection line (SSL) and the ground selection line (GSL). Bit lines (BL) are disposed to intersect the word lines (WL). Each bit line is connected to a drain area through a bit line contact (DC). A common source line (CSL) is disposed between the ground selection lines (GSL). Source regions are electrically connected to each other by the common source line (CSL).
Referring to FIG. 2, which is a plan view illustrating a part of the general NAND type flash memory device, active regions 12 are defined by device isolation layers 15 formed on a semiconductor substrate. The active region 12 extends in a first direction (DA). The ground selection line (GSL), the string selection line (SSL), and the word line (WL) cross over the active region 12 defined by the device isolation layer 15. The word line (WL) and the selection line (GSL, SSL) extend in a second direction (DW) intersecting the first direction (DA) at a right angle. The common source line (CSL) is disposed between the ground selection gate lines (GSL) of adjacent cell strings. The common source line (CSL) crosses over the active region and is electrically connected to the active region thereunder. The active region between the adjacent string selection lines (SSL) is electrically connected to a bit line (not shown) crossing over the word line (WL) by a bit line contact (DC). Floating gates 24, which may be charge storage elements, are disposed in regions where the active regions 12 and the word lines (WL) intersect each other. The floating gate 24 is placed between the active region 12 and the word line (WL). When the active region 12, the word line (WL), a region between the active regions 12, and a region between the word lines (WL) have the same width ‘a’, any floating gate placed at the center is adjacent to two floating gates spaced therefrom at a distance ‘a’ in the first direction (DA), and also adjacent to two floating gates spaced therefrom at a distance ‘a’ in the second direction (DW).
As the memory device becomes highly integrated, parasitic capacitance between the floating gates may increase and may cause malfunctioning of the memory device, such as, for example, a program disturbance between the memory cells.
Referring to FIG. 3, which is a schematic perspective view of a flash memory that illustrates a relation between floating gate voltage and parasitic capacitance, gate structures 37 are placed on active regions 19 that are defined by device isolation layers 22 formed in the substrate 10. The gate structure 37 can have a sequentially-stacked structure of a tunnel oxidation layer 25, a floating gate 29, an ONO layer 32, and a control gate 35. The active region 19 extends in the first direction (DA), and the control gate 35 extends in the second direction (DW) to form a word line. Interlayer insulation layers (not shown) are placed between the gate structures 37 adjacent in the first direction (DA).
Reference signs V and C denote a voltage and capacitance at a corresponding position, respectively. Vfg denotes a voltage of a floating gate of the center of nine floating gates. VA denotes a voltage of each of floating gates adjacent to the center floating gate in the first direction (DA), and VW denotes a voltage of each of floating gates adjacent to the center floating gate in the second direction (DW). Also, Cfga denotes parasitic capacitance generated between the floating gates adjacent in the first direction (DA), and Cfgw represents parasitic capacitance generated between the floating gates adjacent in the second direction (DW).
A word line formed of a conductive layer is interposed between the two floating gates adjacent in the second direction (DW) to prevent the parasitic capacitance (Cfgw). However, since just the interlayer insulating layer is placed between the two floating gates adjacent in the first direction (DA), the parasitic capacitance (Cfgw) may not be effectively prevented. That is, electrical interference caused by the floating gates adjacent in the first direction (DA) can be greater than that of the floating gates adjacent in the second direction. Thus, reliability and operation characteristics of the memory device may be lowered.